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FEATURES Fully Compliant with IS98A and PCS Specifications Linear IF Amplifier -63 dB to +34 dB Linear-in-dB Gain Control Temperature-Compensated Gain Control Quadrature Modulator Modulates IFs from 50 MHz to 350 MHz Integral Low Dropout Regulator Accepts 2.9 V to 4.2 V Input from Battery Low Power 10.4 mA at Midgain <10 A Sleep Mode Operation Companion Receiver IF Chip Available (AD6121) APPLICATIONS CDMA, W-CDMA, AMPS and TACS Operation QPSK Transmitters GENERAL DESCRIPTION
CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator AD6122
range IF amplifiers with voltage-controlled gain and a powerdown control input. An integral low dropout regulator allows operation from battery voltages from 2.9 V to 4.2 V. The gain control input accepts an external gain control voltage input from a DAC. It provides 97 dB of gain control with a nominal 75 dB/V scale factor. Either an internal or an external reference may be used to set the gain-control scale factor. The I and Q modulator accepts differential quadrature baseband inputs from a CDMA baseband converter. The local oscillator is injected at twice the IF frequency. A divide-by-two quadrature generator followed by dual polyphase filters ensures 1 quadrature accuracy. The modulator provides a common-mode reference output to bias the transmit DACs in the baseband converter to the same common-mode voltage as the modulator inputs, allowing dc coupling between the two ICs and thus eliminating the need to charge and discharge coupling capacitors. This allows the fastest power-up and power-down times for the AD6122 and CDMA baseband ICs. The AD6122 is fabricated using a 25 GHz f t silicon BiCMOS process and is packaged in a 28-lead SSOP and a 32-leadless LPCC chip scale package (5 mm x 5 mm).
The AD6122 is a low power IF transmitter subsystem, specifically designed for CDMA applications. It consists of an I and Q modulator, a divide-by-two quadrature generator, high dynamic
FUNCTIONAL BLOCK DIAGRAM
VCC
QUADRATURE MODULATOR OUTPUT QUADRATURE MODULATOR I INPUT
ATTENUATOR
IF AMPLIFIER INPUT
IF AMPLIFIERS LOCAL OSCILLATOR INPUT Q INPUT COMMON-MODE REFERENCE OUTPUT VPOS LOW DROPOUT REGULATOR VREG 2 TRANSMIT OUTPUT
AD6122
GAIN CONTROL SCALE FACTOR
TEMPERATURE COMPENSATION
POWER- POWERDOWN 1 DOWN 2
1.23 V GAIN CONTROL GAIN CONTROL VOLTAGE REFERENCE REFERENCE INPUT OUTPUT VOLTAGE INPUT
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD6122-SPECIFICATIONS1 k(T =. +25 C, V noted) NOTE: All powers shown in dBm are referred to
A
CC
= +3.0 V, LO = 2
IF, REFIN = 1.23 V, LDO Enabled, unless otherwise
Min Typ Max Unit
Specification MODULATOR Output Level Output Third Order Harmonic I/Q Inputs Differential Input Voltage Bandwidth Resistance Quadrature Accuracy Amplitude Balance Output Referred Noise Modulator Common-Mode Reference LO Input Resistance LO Input Capacitance LO Carrier Leakage IF AMPLIFIER Noise Figure Input 1 dB Compression Point Input Third-Order Intercept Gain Flatness Input Capacitance Differential IF Input Resistance Differential IF Output Resistance Differential IF Output Capacitance GAIN CONTROL INTERFACE Gain Scaling Gain Scaling Linearity Minimum Gain Maximum Gain Gain Control Response Time Input Resistance at REFIN Input Resistance at VGAIN POWER-DOWN INTERFACE Logic Threshold High Logic Threshold Low Input Current for Logical High Turn-On Response Time Turn-Off Response Time LOW DROPOUT REGULATOR Input Range Nominal Output Dropout Voltage Reference Output POWER SUPPLY Supply Range Bypassing Internal LDO Supply Current Standby Current OPERATING TEMPERATURE TMIN to TMAX
Specifications subject to change without notice.
Conditions LO = 260.76 MHz (2 x IF), 100 mV p-p 500 mV p-p Differential I and Q Inputs; Output Level Referred to a 1 k Differential Load
-21 -50 500 20 30 1 0.1 -169 1.408 1.2 2.4 -40 10 -32 -24 0.25 2.3 680 4.2 2.0 75 3 -63 +34 0.7 10 109 1.34 1.30 0.1 23 187
dBm dBc mV p-p MHz k dB dBm/Hz V k pF dBc dB dBm dBm dB pF k pF dB/V dB/V dB dB s M k V V A s ns
Differential -3 dB
0.9 MHz to 5.0 MHz Offsets Differential Input at 260.38 MHz Differential Input at 260.38 MHz Bias I/Q Using MODCMREF FIF = 130.38 MHz VGAIN = 2.5 V, 1 k Differential Load VGAIN = 2.5 V VGAIN = 2.5 V IF 630 kHz Shunt Equivalent Model at 130.38 MHz Shunt Equivalent Model at 130.38 MHz Per Pin at 130.38 MHz Per Pin at 130.38 MHz Using Internal Reference For a Typical Dynamic Range of 92 dB VGAIN = 0.5 V VGAIN = 2.5 V 90 dB Gain Change, Min Gain to Max Gain
Power-Up on Logical High
Measure to Settling of AGC from Standby Mode To 200 A Supply Current External PNP Pass Transistor, VCE SAT = -0.4 V Max, hFE = 100/300 Min/Max
2.9-4.2 2.70 200 1.23 2.7-5.0 10.4 7.8 -40 +85
V V mV V V mA A C
VGAIN = 1.5 V (Unity Gain)
-2-
REV. B
AD6122
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage DVCC, IFVCC, TXVCC to DGND, IFGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . 600 mW Operating Temperature Range . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 28-lead SSOP Package: JA = 115.25C/W.
PIN CONFIGURATIONS
SSOP Package
LPCC Package
REFOUT
VGAIN
REFIN
PD2
PD1
PD1 1 PD2 2 LDOE 3 LDOB 4 LDOC 5 LDOGND 6 DGND 7 LOIPP LOIPN
28 VGAIN 27 REFIN 26 REFOUT 25 IFVCC 24 IFGND
IFVCC
LDOE
32 31 30 29 28 27 26 25 LDOB 1 LDOC 2 LDOGND 3 LDOGND 4 DGND 5 LOIPP 6 LOIPN 7 DVCC 8 9
TXOPP
NC
24 IFGND 23 IFGND 22 IIPP
AD6122
TOP VIEW
23 IIPP 22 IIPN
8 (Not to Scale) 21 MODCMREF 9 20 QIPN 19 QIPP 18 MODOPP 17 MODOPN 16 IFINP 15 IFINN
AD6122 Top View (Not to Scale)
21 IIPN 20 MODCMREF 19 QIPN 18 QIPP 17 MODOPP
DVCC 10 TXOPP 11 TXOPN 12 TXVCC 13 IFGND 14
10 11 12 13 14 15 16
IFGND IFGND MODOPN TXOPN TXVCC IFINN IFINP
NC = NO CONNECT
ORDERING GUIDE
Model AD6122ARS AD6122ARSRL AD6122ACP AD6122ACPRL
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description Shrink Small Outline Package (SSOP) 28-Lead SSOP on Tape-and-Reel Chip Scale Package (LPCC) 32-Leadless LPCC on Tape-and-Reel
Package Option RS-28 CP-32
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6122 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
-3-
AD6122
PIN FUNCTION DESCRIPTIONS
SSOP Pin # 1
LPCC Pin # 30
Pin Label PD1
Description Power-Down 1
Function IF Amplifier Power-Down Control Input; CMOS Compatible; HIGH = Entire IC Powers Down, LOW = IF Amplifiers On. Modulator Power-Down Control Input; CMOS Compatible; HIGH = Modulator Off , LOW = Modulator On. Connects to Emitter of External PNP Pass Transistor and VCC. Connects to Base of External PNP Pass Transistor. Connects to Collector of External PNP Pass Transistor. Ground. Ground. Connects to Local Oscillator; AC Coupled. Connects to Ground via Decoupling Capacitor. Connects to Digital Supply. Connects to Output Filter; AC Coupled. Connects to Output Filter; AC Coupled. Connects to LDO Output via Decoupling Network. Ground. IF "Negative" Input from LC Roofing Filter. IF "Positive" Input from LC Roofing Filter. Output Modulator Output to LC Roofing Filter. Modulator Output to LC Roofing Filter. Connects to Q "Positive" Output of Baseband IC. Connects to Q "Negative" Output of Baseband IC. Connects to CDMA Baseband Converter Tx DAC Common-Mode Reference Input. Connects to I "Negative" Output of Baseband IC. Connects to I "Positive" Output of Baseband IC. Connects to IF Ground. Connects to Decoupled Output of LDO Regulator. Provides 1.23 V Voltage Reference Output for DAC in CDMA Baseband Converter and REFIN. Accepts 1.23 V Reference Input from REFOUT or External Reference. Accepts Gain Control Input Voltage from External DAC. Max Gain = 2.5 V; Min Gain = 0.5 V.
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
31 32 1 2 3, 4 5 6 7 8 9 10 11 12, 13 14 15 16 17 18 19 20 21 22 23, 24 25 26 27 28 29
PD2 LDOE LDOB LDOC LDOGND DGND LOIPP LOIPN DVCC TXOPP TXOPN TXVCC IFGND IFINN IFINP MODOPN MODOPP QIPP QIPN MODCMREF IIPN IIPP IFGND NC IFVCC REFOUT REFIN VGAIN
Power-Down 2 Low Dropout Regulator Pass Transistor Emitter Connection Low Dropout Regulator Pass Transistor Base Low Dropout Regulator Pass Transistor Collector Low Dropout Regulator Ground Digital Ground Local Oscillator "Positive" Input Local Oscillator "Negative" Input Digital VCC Transmit Output "Positive" Transmit Output "Negative" Transmit Output VCC IF Ground IF Input "Negative" IF Input "Positive" Modulator "Negative" If Output Modulator "Positive" Output Q Input "Positive" Q Input "Negative" Modulator Common-Mode Reference Out I Input "Negative" I Input "Positive" Ground No Connect IF VCC Gain Control Reference Output Gain Control Reference Input Gain Control Voltage Input
-4-
REV. B
AD6122 Test Figures
0.1 F +15V 8 VP OUT A=1 VN I DATA 50 0.1 F +15V 1 X1 8 VP OUT A=1 VN -15V 5 0.1 F 450 MODOPP 0.1 F +15V 1 X1 MUST BE EQUAL LENGTHS MODCMREF 8 VP OUT A=1 VN Q DATA 50 0.1 F +15V 8 VP OUT A=1 VN -15V 5 0.1 F LOIPP LOIPN 7 50 -15V 5 0.1 F 7 50 MODOPN 10nF 10nF 205 450 MOD_OUT 7 50 -15V 5 0.1 F 7 50 MUST BE EQUAL LENGTHS MODCMREF 1 X1 2 X2 V-1 3 Y1 4 Y2 V-1
IIPP
AD830
AD6122
2 X2 V-1 MODCMREF 3 Y1 4 Y2 V-1
IIPN VREG OUT 0.1 F
AD830
2 X2 V-1 3 Y1 4 Y2 V-1
QIPP 0.1 F VREG OUT
AD830
1 X1 2 X2 V-1 MODCMREF 3 Y1 4 Y2 V-1
MODCMREF QIPN
AD830
LO INPUT
Figure 1. Quadrature Modulator's Characterization Input and Output Impedance Matches
REV. B
-5-
AD6122
VREG OUT PULL-UP INDUCTORS CHOSEN FOR PEAK RESPONSE AT THE TEST FREQUENCY. 1:8 RF SOURCE 383 511 383 10nF IFINN 10nF TXOPN 10nF 453 IFINP TXOPP 10nF 0.1 F 453 205 4:1 TO SPECTRUM ANALYZER
AD6122
0.1 F VREG OUT
Figure 2. IF Amplifier's Characterization Input and Output Impedance Matches
NOTE: RF CABLES FOR I AND Q PATHS MUST BE OF EQUAL LENGTH TEST BED MOTHERBOARD I DATA TEKTRONIX AFG2002 500mVp-p DIFFERENTIAL Q DATA R&S SMT03 Q CHANNEL IFTX OUT LO INPUT RF IF IN AUX MEAS PORT I CHANNEL MOD OUT R&S FSEA20/30 SPECTRUM RF ANALYZER INPUT
RF SOURCE 1
TO RF SWITCHES
R&S SMT03
RF HPE3610 POWER SUPPLY
HP34970A DATA ACQUISITION & SWITCH CONTROL DC MEASUREMENTS & CONTROL BITS
RF SOURCE 2
Figure 3. General Test Set
-6-
REV. B
AD6122
VREG OUT PULL-UP INDUCTORS CHOSEN FOR PEAK RESPONSE AT THE TEST FREQUENCY. NOISE SOURCE REACTIVE CONJUGATE MATCH 1:8 10nF IFINN 10nF TXOPN 10nF 453 IFINP TXOPP 10nF 0.1 F 453 205 4:1 TO NOISE FILTER METER
AD6122
0.1 F VREG OUT
Figure 4. IF Amplifier's Noise Figure Test Set
HP8116A FUNCTION GEN. 4 kHz, 0.5V TO 2.5V SQ. WAVE
ROHDE & SCHWARZ SMT03 100MHz, -30dBm
HP8116A FUNCTION GEN. 4kHz, 0V TO 2.7V SQ. WAVE
ROHDE & SCHWARZ SMT03 100kHz, -30dBm
AGC
IFIN
TEKTRONIX TDS 744A CH 1 WITH X10 PROBE
PD1, PD2
IFIN
TEKTRONIX TDS 744A CH 1 WITH X10 PROBE
IFOUT AD6122 TEST BED
CH 2 WITH COAX CABLE 50
IFOUT AD6122 TEST BED
CH 2 WITH COAX CABLE 50
a. Response Time from Gain Control to IF Output
b. Response Time from PD1 and PD2 Control to IF Output
Figure 5. Response Time Setup
REV. B
-7-
AD6122 -Typical Performance Characteristics
REF LEV -40dBm -40 -50 -60 -70 RBW VBW SWT 1 30kHz 100kHz 2s UNIT dBm A
-30
UNDESIRED SIDEBAND - dBc
-49.18dBm 1 (T1) 130.67458918MHz CH PWR -33.92dBm -77.32dB ACP UP 77.46dB AVE LOW
-35
POWER - dBm
-80 -90 -100 -110 -120 -130 -140 CENTER 130.38MHz 519kHz/DIV SPAN 5.19MHz CL1 CU1
-40
-45 50
100
150 200 250 OUTPUT FREQUENCY - MHz
300
350
Figure 6. Spectral Plot at Modulator Outputs: ACPR
Figure 9. Modulator Output Undesired Sideband vs. Output Frequency
-35
-10
MODULATOR OUTPUT - dBm REFERRED TO A 1k DIFFERENTIAL LOAD
100 150 200 250 FREQUENCY - MHz 300 350
-15
LO LEAKAGE - dBc
-40
-20
-25
-45
-30
-50 50
-35 -14.0
-12.0
-10.0 -8.0 -6.0 MODULATOR, I = Q - dBV
-4.0
-2.0
Figure 7. Modulator LO Leakage vs. Output Frequency
Figure 10. Modulator Gain: Input (dBV) vs. Output (dBm)
-15
OUTPUT DESIRED SIDEBAND LEVEL - dBm REFERRED TO 1k
-45
-20
THIRD HARMONIC - dBc
-50
-25
-55
-30
-60
-35
-40 50
100
150 200 250 OUTPUT FREQUENCY - MHz
300
350
-65 50
100
150 200 250 OUTPUT FREQUENCY - MHz
300
350
Figure 8. Modulator Output Desired Sideband vs. Output Frequency Without Roofing Filter
Figure 11. Modulator Third Harmonic
-8-
REV. B
AD6122
40
-24
20
Load
-25
TA = -40 C -20 TA = +85 C -40
IIP3 - dBm Referred to 1k
0
GAIN - dB With a 1k
-26
-27
-60 TA = +25 C -80 0.5 1.0 1.5 VGAIN - V 2.0 2.5
-28 2.5
2.7
2.9 3.1 3.3 SUPPLY VOLTAGE - V
3.5
3.7
Figure 12. IF Amplifier Response Curve: Gain vs. VGAIN, TA = -40C, +25C, +85C
Figure 15. IF Amplifier Input IP3 vs. Supply Voltage
45 35 25 15 5 GAIN ERROR
6.0
-23
ERROR FROM PREDICTED VALVE - dB
5.0 4.0 3.0 2.0 1.0 0 -1.0 -2.0 GAIN -3.0 -4.0 -5.0 0.9 1.3 1.7 VGAIN - V 2.1 -6.0 2.5
-5 -15 -25 -35 -45 -55 -65 -75 0.5
IIP3 - dBm Referred to 1k
-24
GAIN - dB
-25
-26 50
100
150 200 250 FREQUENCY - MHz
300
350
Figure 13. IF Amplifier Gain and Error vs. VGAIN
Figure 16. IF Amplifier Input IP3 vs. Frequency
5.0
30.0
0
IIP3 - dBm Referred to 1k
NOISE FIGURE - dB
25.0
-5.0
20.0 133MHz 313MHz 15.0 238MHz 10.0
-10.0
-15.0
-20.0
-25.0 0.5
0.9
1.3 1.7 VGAIN - V
2.1
2.5
5.0 -10.0
0
10.0 20.0 GAIN - dB
30.0
40.0
Figure 14. IF Amplifier Input IP3 vs. VGAIN
Figure 17. IF Amplifier Noise Figure vs. Gain
REV. B
-9-
AD6122
40 VGAIN = 2.5V 20 VGAIN = 2.0V 0
GAIN - dB TOTAL CURRENT CONSUMPTION - mA
18.0
16.0
14.0
-20
VGAIN = 1.5V
12.0
-40 VGAIN = 1.0V -60 VGAIN = 0.5V -80 50 100 150 200 250 FREQUENCY - MHz 300 350
10.0
8.0 0.5
1.0
1.5 VGAIN - V
2.0
2.5
Figure 18. IF Amplifier Gain vs. Frequency for VGAIN = 2.5 V, 2.0 V, 1.5 V, 1.0 V
Figure 19. Total Current Consumption vs. VGAIN
REF LEV -30dBm -30 -40 -50 -60
POWER - dBm
RBW VBW SWT
30kHz 300kHz 2s
UNIT
dBm A
1
1
-46.78dBm 1 (T1) 130.38000000MHz CH PWR -31.93dBm -66.95dB ACP UP AVE LOW -68.95dB -0.28 dB 1 (T1) 330.66132265kHz
-70 -80 -90 -100 -110 -120 -130 CENTER 130.38MHz 600kHz/DIV SPAN 6MHz CL1 CO CO CU1
Figure 20. ACPR of Cascaded Modulator, 20 dB Pad and IF Amplifier: Spectral Plot
-10-
REV. B
AD6122
VCC
QUADRATURE MODULATOR OUTPUT QUADRATURE MODULATOR I INPUT
ATTENUATOR
IF AMPLIFIER INPUT
IF AMPLIFIERS LOCAL OSCILLATOR INPUT Q INPUT COMMON-MODE REFERENCE OUTPUT VPOS LOW DROPOUT REGULATOR VREG 2 TRANSMIT OUTPUT
AD6122
GAIN CONTROL SCALE FACTOR
TEMPERATURE COMPENSATION
POWERDOWN 1
POWERDOWN 2
1.23 V REFERENCE OUTPUT
GAIN CONTROL REFERENCE VOLTAGE INPUT
GAIN CONTROL VOLTAGE INPUT
Figure 21. Block Diagram
THEORY OF OPERATION IF Amplifiers and Gain Control
The CDMA Transmitter IF Subsystem (Figure 21) consists of an I and Q modulator with a divide-by-two quadrature generator, high dynamic range IF amplifiers with voltage-controlled gain, a low dropout regulator and power-down control inputs.
I and Q Modulator
The I and Q modulator accepts differential quadrature baseband inputs from CDMA baseband converters. The LO is injected at twice the IF frequency. A divide-by-two quadrature generator followed by dual polyphase filters ensures 1 quadrature accuracy (Figure 22). For 500 mV p-p differential I and Q input signals, the output power of the modulator will be -21 dBm referred to 1 k when the output of the modulator is loaded with a 1 k differential load. With the maximum input conditions stated above, the modulator outputs are a 225 A p-p differential current; consequently, the output load will greatly affect the output power of the modulator.
2 IF LO INPUT I
The IF amplifiers provide an 86 dB linear in dB gain control range. The input stage uses a differential, continuously variable attenuator based on Analog Devices' patented X-AMPTM topology. This low noise attenuator consists of a differential R-2R ladder network, linear interpolator and a fixed gain amplifier. The IF amplifier's input impedance is 1 k differential. Similar to the I and Q modulator's output, the IF amplifier's output is a differential current, which will vary depending upon the gain control voltage. In order to achieve the specified gain, the output of the IF amplifiers should be loaded with a 1 k differential load. The gain control circuits contain both temperature compensation circuitry and a choice of internal or external reference for adjusting the gain scale factor. The gain control input accepts an external gain control voltage input from a DAC. It provides 97 dB of gain control range with a nominal 75 dB/V scale factor. The external gain control input signal should be a clean signal. It is recommended to filter this signal in order to eliminate the noise that results from the DAC. If a noisy signal is used for the gain control voltage, VGAIN inband and adjacent channel noise peaking can occur at the output of the AD6122. A simple RC filter can be employed, but care should be taken with its design. If too big a resistor is used, a large voltage drop may occur across the resistor, resulting in lower gain than expected (as a result of a lower voltage reaching the AD6122). An RC filter with a 20 kHz bandwidth, employing a 1 k resistor is appropriate. This results in an 8.2 nF capacitor. The resulting circuit is shown in Figure 23. Note that the input resistance at the VGAIN pin is approximately 100 k.
FROM BASEBAND CONVERTER 1k 8.2nF
2
I POLYPHASE FILTERS QUADRATURE OUTPUT TO MODULATOR Q
180
2
Q
Figure 22. Simplified Quadrature Generator Circuit
The I and Q modulator also provides a common mode reference signal at the MODCMREF pin. This voltage is a dc voltage set to 1.408 V when a 2.7 V supply is used. It is used to dc bias the output of the DAC that provides I and Q inputs to the modulator.
AD6122
VGAIN 109k
X-AMP is a trademark of Analog Devices, Inc.
Figure 23. Gain Voltage Filtering
REV. B
-11-
AD6122
The AD6122's overall gain, expressed in decibels, is linear in dB with respect to the automatic gain control (AGC) voltage, VGAIN. Either REFOUT or an external reference voltage connected to REFIN may be used to set the voltage range for VGAIN. When the internal 1.23 V reference, REFOUT, is connected to REFIN , VGAIN will control the entire AGC range when it is typically set between 0.5 V and 2.5 V. Minimum gain occurs at minimum voltage on VGAIN and maximum gain occurs at maximum voltage on VGAIN. The maximum and minimum gain will not change with a change in voltage at REFIN. Rather, the slope of the gain curve will change as a result of a change in the required range for VGAIN. Figure 24 shows the piecewise linear approximation of the gain curve for the AD6122. up. The control is provided via two control pins, PD1 and PD2. Table I shows the operating modes of the AD6122.
Table I. Operating Modes
PD1 0 0 1 1
PD2 0 1 0 1
IF Amp ON ON INVALID STATE OFF
Modulator ON OFF INVALID STATE OFF
Low Dropout Regulator
MAXIMUM GAIN
MINIMUM GAIN
The AD6122 incorporates an integrated low dropout regulator. The regulator accepts inputs from 2.9 V to 4.2 V and supplies a constant 2.7 V reference output at LDOC. The 2.7 V signal can be used to provide the dc voltages required for the DVCC, TXVCC and IFVCC dc supplies. In order to configure the low dropout regulator, an external pass transistor is required. A pnp bipolar junction transistor with a minimum hFE of 100 and a maximum hFE of 300 and a VCESAT of -0.4 V is required. In order to use the low dropout regulator, configure the transistor as shown in Figure 25. The 18 pF capacitor in Figure 25 is used for decoupling the 2.7 V dc signal. In addition to the low dropout regulator, a band-gap voltage reference produces a 1.23 V reference voltage at REFOUT. This reference voltage will be present whenever a 2.7 V dc signal is present on pin LDOC. This 1.23 V reference voltage can then be used to provide the gain reference signal required for REFIN and the reference voltage for the transmit DACs in a baseband converter.
AD6122
GAIN - V/V
VGAIN - V
Figure 24. Piecewise Linear Approximation for the AD6122 Gain Curve
Because the minimum and maximum gain from the AD6122 are constant, we can approximate the VGAIN range for a given REFIN voltage by using Equation 1.
VGAIN = (GAIN - MinGain) x 1.6REFIN + 0.4 REFIN MaxGain - MinGain
(1)
2.9V - 4.2V PASS TRANSISTOR 2.7V 18pF REFOUT 1.23V LDOE
Where MaxGain is the maximum gain (+34 dB) in dB, MinGain is the minimum gain (-63 dB) in dB, REFIN is the reference input voltage, in volts, VGAIN is the gain control voltage input, in volts, and GAIN is the particular gain, in dB, we would have for a given REFIN and VGAIN. Consequently, for any REFIN we choose, we can calculate the VGAIN range by solving Equation 1 for VGAIN. For example, in order to determine the VGAIN value for the maximum gain condition, given a 1.23 V REFIN, we can solve Equation 1 for VGAIN by substituting +34 dB for GAIN and MaxGain, -63 dB for MinGain and 1.23 V for REFIN. VGAIN can then be calculated to be 2.46 V, or approximately 2.5 V. For the minimum gain condition, we can determine the VGAIN value by substituting 34 dB for MaxGain, -63 dB for GAIN and MinGain and 1.23 V for REFIN. VGAIN can then be calculated to be 0.492 V or approximately 0.5 V.
Power-Down Control
LDOB LDOC
Figure 25. Configuring the Low Dropout Regulator
It is possible to bypass the low dropout regulator on the AD6122 and use an external regulator instead. In order to bypass the integrated low dropout regulator, connect pins LDOE, LDOB and LDOC together and then connect them all to the 2.7 V external regulator voltage. This configuration is shown in Figure 26. Even when the low dropout regulator is bypassed, the 1.23 V reference voltage at pin REFOUT is still present.
The AD6122 can be operated with the IF amplifiers and quadrature modulator both powered up, both powered down or with the IF amplifiers powered up and the modulator powered down. The AD6122 cannot operate with only the modulator powered
-12-
REV. B
AD6122
AD6122
LDOE FROM EXTERNAL VOLTAGE REGULATOR
The attenuator is discussed in the next section entitled Measuring Adjacent Channel Protection Ratio (ACPR). In order to confirm whether the roofing filter has been correctly designed, sweep the LO frequency and view the output of the IF amplifier on a spectrum analyzer. The signal should peak at the IF frequency if the inductor value is correct. The Q of the filter should be low enough so that variations in the parasitic capacitances should be negligible.
LDOB
LDOC
REFOUT
1.23V
Figure 26. Configuration for Bypassing the Low Dropout Regulator
ROOFING FILTER
The value of inductor required will be a function of the IF frequency at which we are operating. The values of inductors used during characterization at Analog Devices are shown in Table II. Because the exact value will also be a function of printed circuit board layout, we will have to vary the value from those in Table II to those required for our board.
Table II. Roofing Filter Inductor Values
Because the outputs of the AD6122 modulator are open collector, the parasitic capacitances seen at the output of the modulator, and inputs of the IF amplifiers, are high enough to create a low-pass filter, which may attenuate the IF signal. Consequently, the parasitic capacitance must be cancelled by using external inductors to form a parallel resonant circuit. The external inductors and the internal parasitic capacitors form what is known as the roofing filter, with the resonant frequency given by Equation 2.
IF Frequency (MHz) 50-125 126-200 201-275 276-350
Value of Roofing Filter Inductor (nH) 470 150 68 27
f0 =
1 2 LCPAR
(2)
where f0 is the IF frequency, in Hertz, CPAR is the total parasitic capacitance in Farads, and L is the value of external inductors, in henrys. The roofing filter may be composed of the pull-up inductors required on the open collector outputs of the I and Q modulator. This configuration is shown in Figure 27. The 10 nF capacitors are used for ac coupling.
It should be noted that the roofing filter is only required when cascading the output from the I/Q modulator to the input of the IF amplifiers. If we are driving into the IF amplifiers directly, no roofing filter is required, however, pull-up inductors are required in order to set the dc voltage of the open collector modulator outputs.
MEASURING ADJACENT CHANNEL POWER RATIO (ACPR)
AD6122
MODOPP 2CPAR L/2 VCC
At maximum IF gain and specified input conditions (500 mV p-p baseband inputs), the output of the I/Q modulator is 11 dB greater than the P1 dB (one dB compression point) of the IF amplifiers. This configuration maximizes the ratio of signal to LO feedthrough and also maximizes the signal to noise ratio. Once these ratios are maximized, we can attenuate the noise, signal and LO feedthrough without affecting the ratios. Therefore, attenuation is required between the I/Q modulator and the IF amplifiers. In order to determine exactly how much attenuation is required, we must recognize that ACPR is a function of the attenuation from the modulator outputs to the IF amplifier inputs. As a result, in order to determine how much attenuation is required, we must first know how good an ACPR performance is desired. If too much attenuation is applied, the ACPR will be very good, but, the IF amplifier's output power level will be low, possibly resulting in poor signal to noise ratio and possibly requiring additional amplification external to the AD6122. An appropriate method that can be used to provide the correct amount of attenuation between the modulator outputs and the IF amplifier inputs is a simple differential voltage divider. The topology and its design equations are shown in Figure 28 and Equations 3 and 4. The input impedance of the IF amplifiers is typically 1 k. As a result, if we design resistor R2 to be much less than 1 k, we can neglect the effects of the IF amplifier's input impedance on the attenuator.
2CPAR MODOPN
L/2
10nF PARALLEL RESONANT CIRCUIT 10nF
IFINN
IFINP 10nF ATTENUATOR
Figure 27. Roofing Filter Configuration
REV. B
-13-
AD6122
AD6122
MODOPP R1 IFINP
This circuit is very sensitive to parasitic capacitances. As a result, extra care should be taken to ensure minimum and equal printed circuit board transmission lines. We should also try to keep R2 small in order to minimize the effects of printed circuit board parasitic capacitance on loading the output of the pad. In conclusion, we have to develop a system-level ACPR budget for our radio, and from that budget determine how much ACPR performance we desire from the AD6122. We then need to implement the appropriate attenuation network to get that ACPR performance.
LEVEL DIAGRAM
ZIN MODOPN R1
R2 IFINN
RSHUNT >>R2
Figure 28. Pad Topology
1 R1 L = 20 log 1 1 + R1 R2 / 2
Z IN = 2R1+ R2
(3)
(4)
where L is the transducer loss (or loss through the pad) in dB and ZIN is the desired input resistance in ohms. Using these equations, we can design the attenuator circuit to provide whatever amount of attenuation we require.
Figure 29 is provided to better understand the different voltage levels you can expect to see at different points of the AD6122. It represents the voltage and power levels expected for a maximum input condition of 500 mV p-p at the I and Q modulator and maximum gain in the IF amplifiers. When trying to make these measurements, a high impedance (10 M) active FET probe (for example, the Tek P6204, from Tektronix) should be used to minimize the effects of loading the circuit with the probe. In order to produce these results, the attenuator is designed to have a 1 k input impedance and the output of the IF amplifiers are loaded with 1 k. The roofing filter is designed to resonate the parasitic capacitance at the IF frequency.
MODULATORS I 500mV p-p DIFFERENTIAL LO 2 100mV p-p DIFFERENTIAL Q 500mV p-p DIFFERENTIAL -21dBm (REFERRED TO 1k ) 252.1mV p-p DIFFERENTIAL MODOP VCC -41dBm (REFERRED TO 1k ) 25.21mV p-p IF AMPLIFIERS DIFFERENTIAL IFIN -7dBm (REFERRED TO 1k ) 1.263V p-p DIFFERENTIAL TRANSMIT OUTPUT
VGAIN = 2.5V GAIN = +34dB 1k 20dB ATTENUATOR ZIN = 1k ZOUT = 1k
Figure 29. Level Diagram
-14-
REV. B
AD6122
INPUT INTERFACES
The AD6122 interfaces to CDMA baseband converters providing either IF or baseband outputs. The baseband input is provided by direct connection of the baseband converter's baseband output to the baseband input of the AD6122 (Figure 30). The IF amplifier's gain control is provided by connection of the transmit AGC DAC's output on the baseband converter, through a low-pass filter to the VGAIN pin on the AD6122.
PD1 TEMPERATURE COMPENSATION GAIN CONTROL SCALE FACTOR
VGAIN TX AGC DAC REFIN EXT REF IN
PD2
VCC
LDOE LDOB LDOC LDOGND LOW DROPOUT REGULATOR REFOUT IFVCC IFGND IIPP I OUTPUT Q LOIPP LOIPN I DVCC QIPN QIPP MODOPP MODOPN 2 IIPN MODCMREF I OUTPUT VCM REF IN Q OUTPUT Q OUTPUT
DGND
AD6122
VCC
VCC
CDMA BASEBAND IC
TXOPP TXOPN TXVCC IFGND
IFINP
IFINN
Figure 30. Typical Connections to Baseband IC Using I and Q Inputs with SSOP Package
REV. B
-15-
AD6122
AD6122 Evaluation Board
The AD6122 Evaluation Board consists of an AD6122, I/O connectors, a 20-pin dual header, 2-pin headers and four AD830 high speed video difference amplifiers. It allows the user to evaluate the AD6122's IF amplifier and modulator together or separately. Because the AD6122 may be used at any IF from 50 MHz to 350 MHz, pads are provided on the LOIPP input, TXOP output, MODOP output and IFIP inputs to allow the user to add matching networks. The board is configured for an IF frequency of 130.38 MHz when shipped. There is no difference between the configuration of the boards with the SSOP or LPCC package. The AD830s are used to provide single-ended to differential conversion and the appropriate phase shift for the I and Q data input pins. As a result, a single-ended signal generator can be used to generate these signals. In order to test the power-down modes of the AD6122, locate the two pin headers on the AD6122 evaluation boards labeled PD1 and PD2. By open-circuiting the pins labeled PD1, the IF amplifiers power down. By open-circuiting the pins labeled PD2, the modulator powers down. Note that the IF amplifiers and modulator are powered down unless the pins on the two pin headers, PD1 and PD2, are short circuited. The IF input port impedance match used during characterization of the AD6122 at Analog Devices is as follows:
AD6122
50 1:8 383 511 SIGNAL GENERATOR 383 IFINN IFINP
The IF output port impedance match used during characterization at Analog Devices is as follows:
AD6122
TXOPP 453 205 TXOPN 453 SPECTRUM ANALYZER 4:1 50
1k
Figure 32. IF Output Port Impedance Match Used During Characterization at ADI
This is a broadband lossy output match for the 50 MHz to 350 MHz frequency range. The 4:1 ratio in Figure 32 is an impedance ratio and not a voltage ratio. As shipped, the board is configured as follows: 1. J1 is open and J2 is shorted. This enables the LDO regulator. The external PNP transistor should remain in place even when the regulator is bypassed (the Pin LDOB is pulled up by the transistor). 2. X11, X25, X18 and X26 are shorted and X12, X14, X19 and X21 are opened in order to connect the output of the modulator to the input of the IF amplifiers. 3. L4 and L5, the roofing filter components are optimized for an IF frequency of 130.38 MHz. 4. R14, R15 and R16 set the attenuation between the modulator outputs and the IF amplifier inputs to 20 dB. 5. PD1 and PD2 are pulled low by the jumpers on the two pin headers. To power down the chip, set PD1 and PD2 high by removing the jumpers. In order to look at the modulator and IF amplifiers separately, disconnect the output of the modulator from the input of the IF amplifiers. This is accomplished by short circuiting X12, X14, X19 and X20 and open circuiting X11, X18, X25 and X26.
1k
Figure 31. IF Input Port Impedance Match Used During Characterization at ADI
This is a broadband lossy match used for characterization over the 50 MHz to 350 MHz frequency range. All dBm references in the characterization data collected using this match are referenced to 1 k. Note that the 1:8 ratio in Figure 31 is an impedance ratio and not a voltage ratio.
-16-
REV. B
AD6122
Table III describes the high frequency signal connectors on the AD6122 customer sample boards.
Table III. Evaluation Board SMA Signal Connector Description
Table IV lists the connections for the 20-pin power-supply connector.
Table IV. 20-Pin Power Supply Connection Information
Pin # Connector I CH Description I Modulator Input. 250 mV p-p into 50 termination, dc coupled. The level shifting and phase splitting is done on board by the AD830 amplifiers. Q Modulator Input. 250 mV p-p into 50 termination, ac coupled. The level shifting and phase splitting is done on board by the AD830 amplifiers. Modulator Output. The differential-to-single ended conversion is performed by a balun on the board. Impedance matched to 50 for 130.38 MHz IF frequency. IF Amplifier Input. Single-ended-to-differential conversion performed by a balun on board. Impedance matched to 50 for 130.38 MHz IF frequency. IF Amplifier Output. Differential-to-singleended conversion performed by a balun on board. Impedance matched to 50 for 130.38 MHz IF frequency. Local oscillator positive input at 2 x IF frequency. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Function VPOS for AD6122; 2.9 V to 4.2 V using regulator; 2.7 V to 4.2 V bypassing regulator. VPOS for AD6122; 2.9 V to 4.2 V using regulator; 2.7 V to 3.6 V bypassing regulator. Ground. Ground. Ground. Regulated Output or Input Voltage; Connects to Pin 5 on AD6122. Ground. Ground. Ground. Ground. Ground. PD1; Power-Down 1 Input. Ground. 1.23 V Reference Voltage from AD6122. Ground. VGAIN; Gain Control Voltage Input. -15 V Supply for AD830 Differential Amplifier. +15 V Supply for AD830 Differential Amplifier. MODCMREF; common-mode reference output for baseband converter common-mode reference input. PD2; Power-Down 2 Input.
Q CH
MODOP
IFIP
TXOP
LOIPP
A schematic diagram of the evaluation board is on the next two pages.
REV. B
-17-
AD6122
AD6122
PD1 PD2 VPOS 2.9V - 4.2V J2 0 FMMT4403CT-ND LDOE Q1 LDOB LDOC LDOGND DGND X2 0 LOIPP X1 X3 C24 0.1 F VCC C1 10nF C2 10nF LOIPP LOIPN DVCC L2 220nH DVCC TXOPP TXOPN TXVCC L3 220nH C25 10nF TXVCC IFGND REFOUT C29 10nF J1 VREG OUT C23 18pF IFVCC IFGND IIPP IIPN MODCMREF QIPN QIPP MODOPP MODOPN IFINP IFINN C11 10nF R14 = 442 R15 = 100 R16 = 442 R14 X18 0 X26 0 C8 10nF C10 10nF C9 10nF X12 X13 X14 L6 C30 R13 R15 R16 X23 27nH IFIP X22 56nH X24 X21 T3 X25 0 T2 IIPP VREG OUT IIPN MODCMREF QIPN QIPP 8:1 C27 10nF C26 10nF VREG OUT IFVCC REFOUT PD1 PD2 VGAIN REFIN R12 0 C28 10nF VGAIN
L4 180nH
L5 180nH X16 100nH X15 4pF X17 MODOP
X5 100nH TXOP X4 X6 3pF
1:8
X8 C3 10nF 0 X7 X9
T1
X10 C4 0 10nF VCC
X11 0
X19 X20
8:1
Figure 33. Schematic Diagram of the Evaluation Board
-18-
REV. B
AD6122
C15 0.1 F +15V 1 2 MODCMREF 3 4 V-1 5 ICH R6 50 -15V C16 0.1 F C17 0.1 F +15V 1 2 MODCMREF 3 4 V-1 5 -15V C18 0.1 F V-1 8 U3 A=1 7 R8 50 1 2 TO IIPN MODCMREF 3 4 V-1 5 -15V C22 0.1 F V-1 +15V 8 U5 A=1 7 V-1 A=1 7 8 SOIC PACKAGE U2 R7 50 1 2 TO IIPP MODCMREF 3 4 V-1 5 QCH R9 50 -15V C20 0.1 F C21 0.1 F V-1 A=1 7 +15V 8 SOIC PACKAGE U4 R10 50 TO QIPP C19 0.1 F
AD830
AD830
R11 50
TO QIPN
AD830
AD830
TO TXVCC
C6 18pF
R1 10 C13 0.01 F
VREG OUT
P1 1 3 5
VPOS
P2 2 4 6 8 10 12 14 16 18 20
L1 470nH R4 10k R5 10k
FROM VPOS 2.9V-4.2V
TO DVCC
VREG OUT
C5 18pF
R2 10 C12 0.01 F R3 10 C14 0.01 F
7 9 11 13
PD1 REFOUT VGAIN +15V PD2 PD1 PD2
TO IFVCC
C7 18pF
15 -15V MODCMREF 17 19
NOTES: 1. TO USE THE LDO REGULATOR, SHORT J2 AND OPEN J1. 2. TO BYPASS THE REGULATOR, SHORT J1 AND OPEN J2 3. TO CONNECT THE OUTPUT OF THE MODULATOR TO THE INPUT OF THE IF AMP, SHORT J5 AND J6. TO TEST THE MODULATOR AND THE IF AMP SEPARATELY, OPEN J5 AND J6. 4. INDICATES A 50 TRACE.
Figure 34. Schematic Diagram of the Evaluation Board
REV. B
-19-
AD6122
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SSOP (RS-28)
0.407 (10.34) 0.397 (10.08)
28
15
1
14
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC
8 0.015 (0.38) SEATING 0.009 (0.229) 0 0.010 (0.25) PLANE 0.005 (0.127)
0.03 (0.762) 0.022 (0.558)
32-Leadless Chip Scale Package (LPCC) (CP-32)
0.205 (5.20) 0.197 (5.00) SQ 0.189 (4.80)
25 24
0.128 (3.25) 0.106 (2.70) SQ 0.049 (1.25)
32 1
PIN 1 INDICATOR 0.015 (0.38) 0.012 (0.30) 0.009 (0.23)
BOTTOM VIEW
17 16
8 9
0.138 (3.50) BSC 0.010 (0.25) REF 0.020 (0.50) BSC 0.039 (1.00) 0.035 (0.90) 0.031 (0.80) 0.002 (0.05) 0.001 (0.02) 0.000 (0.00)
0.018 (0.45) 0.016 (0.40) 0.014 (0.35)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS DIMENSIONS MEET JEDEC MO-220-VHHD-2
-20-
REV. B
PRINTED IN U.S.A.
C00946a-.5-6/00 (rev. B)
0.311 (7.9) 0.301 (7.64)
0.212 (5.38) 0.205 (5.21)

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